1. Field of the Invention
The present invention relates generally to a semiconductor memory device, more particularly to a data outputting circuit for reading data from a semiconductor memory device.
2. Description of the Related Art
Recent advances in the operational speeds of central processing units have fueled the demand for semiconductor memory devices having higher integrations and faster operational speeds. To achieve this demand, data outputting circuitry for reading cell information from a semiconductor memory device needs to operate at faster speeds.
FIG. 1 illustrates a conventional data outputting circuit incorporated in a semiconductor memory device. A switching circuit 1 is connected to a pair of data buses DB and /DB. Cell information is read from one of memory cells in the memory device. The cell information is then provided as a pair of complementary data to the data outputting circuit of the memory device via the switching circuit 1 and the data buses DB and /DB. The data buses DB and /DB are connected to a load circuit 2 including five P channel MOS transistors Tr1 to Tr5 and two resistors R1 and R2.
The transistor Tr1 has a source connected to a power supply V.sub.CC and a drain connected to the data bus DB via the transistor Tr3. The gate and drain of transistor Tr3 are connected to each other. The transistor Tr2 has a source connected to the power supply V.sub.CC and a drain connected to the data bus /DB via the transistor Tr4. The transistor Tr4 has its gate and drain connected to each other. The data buses DB and /DB are connected to each other via the transistor TR5. The gates of the transistors Tr1, Tr2 and Tr5 are supplied with a sense amplifier enable signal LE.
The data buses DB and /DB are connected to ground via the resistors R1 and R2, respectively. Each of the resistors R1 and R2 has a resistance value to prevent the voltage potential of the associated data bus DB or /DB from being raised to the high potential V.sub.CC by releasing, through the resistor R1 or R2, the tailing current of the transistor Tr3 or Tr4 (i.e., the current when the voltage V.sub.GS between its gate and source is zero).
The data buses DB and /DB are connected to a sense amplifier 3 with current mirror circuit configuration. The sense amplifier includes two P channel MOS transistors Tr6 and Tr7 and four N channel MOS transistor Tr8 to Tr11.
As shown in FIG. 1, the transistor Tr6 has a source connected to the power supply V.sub.CC and a drain connected to the gates of the transistors Tr8 and Tr9 and to the drain of the transistor 8. The source of the transistor Tr8 is connected to the data bus DB. The transistor Tr7 has a source connected to the power supply V.sub.CC and a drain connected to the drain of the transistor Tr9. The source of the transistor Tr9 is connected to the data bus /DB.
The data bus DB is connected to the drain of the transistor Tr10 whose source is grounded. The data bus /DB is connected to the drain of the transistor Tr11 whose source is grounded. The gates of the transistors Tr6 and Tr7 are supplied with an inverted sense amplifier enable signal /LE which is an inverted signal of the signal LE. The gates of the transistor Tr10 and Tr11 are supplied with the sense amplifier enable signal LE.
In the sense amplifier 3, the transistors Tr6 and Tr7 form the first current mirror pair, the transistors Tr8 and Tr9 form the second current mirror pair and the transistors Tr10 and Tr11 form the third current mirror pair. The drains of the transistors Tr7 and Tr9 are connected to an output terminal T.sub.0 of the semiconductor memory device. Output data D.sub.OUT is produced at the output terminal T.sub.0.
The resistance RV6 of the transistor Tr6 when turned on is equal to the resistance RV7 of the transistor Tr7 when turned on. The resistance RV8 of the transistor Tr8 when turned on is equal to the resistance RV9 of the transistor Tr9 when turned on. The resistance RV10 of the transistor Tr10 when turned on is equal to the resistance RV11 of the transistor Tr11 when turned on. Accordingly, the resistance values RV6 to RV11 satisfy the following equation (1). EQU RV6:RV8:RV10=RV7:RV9:RV11 (1)
When the sense amplifier enable signal goes high and the signal /LE goes low, the transistors Tr6, Tr7, Tr10 and Tr11 turn on and the sense amplifier 3 is enabled. The data buses DB and /DB then have the voltage potential determined by dividing the potential difference between the supply voltage V.sub.CC and the ground level, following the resistance ratio represented in the equation (1). With this condition, when cell data is read from a memory cell, a slight separation of the voltage potentials of the data buses DB and /DB occurs.
When the voltage potential of the data bus DB is higher than that of /DB, the current through the drain of the transistor Tr8 decreases and the current through the drain of the transistor Tr9 increases. This lowers the voltage potential of the terminal T.sub.0, resulting in setting the output data signal D.sub.OUT low.
In contrast, when the voltage potential of the data bus DB is lower than that of /DB, the current through the drain of the transistor Tr8 increases and the current through the drain of the transistor Tr9 decreases. This raises the voltage potential of the terminal T.sub.0, resulting in setting the output data signal D.sub.OUT high.
The above described data outputting circuit enters into the standby state when the sense amplifier enable signal LE is set low and the signal /LE is set high.
When the data outputting circuit is in the standby state, the transistors Tr6, Tr7, Tr10 and Tr11 are turned off so that the sense amplifier 3 becomes disabled, and the transistors Tr1, Tr2, Tr5 are turned on so that the load circuit 2 becomes enabled. In this case, the data buses DB and /DB have a voltage potential set lower than the supply voltage V.sub.CC by the threshold voltage of the transistor Tr3 or Tr4.
When the sense amplifier enable signal LE goes high and the signal /LE goes low, the transistors Tr1, Tr2 and Tr5 are turned off so that the load circuit 2 becomes disabled, and the transistors Tr6, Tr7, Tr10 and Tr11 are turned on so that the sense amplifier 3 becomes enabled. With this condition, when cell data is read onto the data buses DB and /DB, an output data signal D.sub.OUT according to the cell data is output from the terminal T.sub.0 of the sense amplifier 3.
According to the conventional data outputting circuit, when cell data is read successively, the load circuit 2 stays disabled and the sense amplifier 3 stays enabled. As shown in FIG. 2, when one of the data buses DB and /DB goes low from high and the other goes high from low in synchronism with a change in cell data, it takes a reading period of time t1 for the output data signal D.sub.OUT to go, for example, from low to high.
When the data outputting circuit is in the standby state, the load circuit 2 stays enabled and the sense amplifier 3 stays disabled. In this case, the data buses DB and /DB have a voltage potential set lower than the supply voltage V.sub.CC by the threshold voltage of the P channel MOS transistor Tr3 or Tr4. When the data outputting circuit starts reading operation from the standby state, the voltage potential of each data bus falls to the voltage potential determined by the resistances of the transistors of the sense amplifier 3 when turned on. Specifically, a difference of potential levels develops between the data buses DB and /DB when cell data is read to the data buses DB and /DB. Then, the sense amplifier 3 operates to output the data signal D.sub.OUT according to the read cell data. In this case, it takes an operational period of time t2 for the output data signal D.sub.OUT to go, for example, from low to high.
In general, the operational time t2 is much longer than the reading time t1. There is a time lag t3 between t1 and t2. The time lag t3 corresponds to the time taken when the voltage potentials of the data buses DB and /DB falls from a reset potential V.sub.RESET (i.e., an initial voltage potential in the standby state) to respective voltage potentials during reading operation. Hence, as described above, the operational speed of the conventional data outputting circuit is slow at the initial stage of reading operation, i.e., when shifting from the standby state to the reading operation.